08/25/94 15:00 11'9106680101 analog devices ~ 002/005 --. computer labs ..'! lilli analog devices dgm-1040 and -1080 of a deg litchers general deglitchers are normally used to eliminate the non-linear effects of "glitches" from the output of d/a converters. the computer labs dgm series of deglitchers may be used with almost any type of d/a converter to generate an out- put signal with extremely high spectral purity. these deglitchers have been used for television signal. reproduction, crt displays. wave- i form generation, and automatic test i equipment, to name a few. i i ! ! the problem in most instances, fast-settling di a converters are current-switch- ing types, rather than voltage types. in this type of converter, any input bit changing causes a change in the output current of the converter. the input circuits for current- switching 01 a's, and their ttl or dtl driving logic, are subject to the characteristic of saturated logic which causes propogation delay for negative-going inputs to be dif- ferent from the delay for positive- going inputs. as a result of this phenomenon, time skew of the individual current switches within the d/a converter is worst when one or more input bits are out of phase with th e others. this is true even for ideal inputs in which the digital input bits arrive simultaneously; if there is time skew among the bit inputs, the problem becomes even more pro- nounced. these differences among the internal switches cause a discon- tinuity or "glitch" in the output current of the d/a converter. the true "worst case" glitch always occurs at the switching point of the most significant bit (ms8) or the center point of the output range, because nearly equal and opposite currents are bei ng switched. in addition to this inescapable switching transient in the output, featu res . 15 nsee acquisition time. . 0.01% linearity. . directly interfaces with ultra high-speed, current-output d/a's. . ttl or ecl compatible. . dgm plus d/a costs less than any "degfitched" o/a available, .f:'!. -,sw t squrc j.. .l "~ju~-t:-v--- - - - - -- - - - -0-;"- ;o;u~ - - - - ' 1 i us o.lw rl h--f>-{ $0 :11 .."~. m :!: lauo,( it: ':~~~~"':'- :: i zl: a.': 0tit aut u - -i ""aloo ," -, 50 i i. ~""'v ~'-"... ~ .5v ben(') 1'0 ~ -o.zv i i -5.lv _5~ - -l~ " j, i.o.12,16.z0 ~ ~o"'t1:. '.'1 cl (cl ttl/cl coiov(li'i'co ici'ticd1&j,j to d/& 0iitf'ut -$~ v - , lsc".. ~- !i --------- " ~ 'm:t~ t. ..""ust : si.i ocllted "fusca. "~r 0- ttl . - is w ""'1 i) ., ",,1: ,. td(s[ pi"o uduso if (cl .i'\it optia. 1$ $(lectd. dgio4 series 8l.ocio: d iagra.ioi - -- - - obsolete
08/25/94 15:01 'a'9106680101 most current-output d/a converters also have a maximum output voltage limitation. part of this limitation may be the result of high output capacit- ance and/or resistance; this char- acteristic can be "masked" in data sheets if settling time is specified with an impractically-low imped- ance load. even d/a converters which have low output capacitance and/ or resistance will have a maximum output voltage limitation which is established by saturation of the internal switching transistors. this internal saturation, in turn, generally precludes operating the current-switching d/a con- verter as effectively in a unipolar mode as it can be operated in a bi- polar output mode. note;.: addlt;o~al d.f.il. on 'ha cnar8ct~(i~'ic5 cf current- ,wltchi~!i. r85i...nli~g o/a con'~r!." ore i~cl1jded i~ "nol.. on f""$ettll~g d/a co~.erters'. which 8'. pan 01 ih. oale sneel on ihe compu'er lab. mdsfmdp $e,les o/a's. the solution when first exposed to the un- desirable effect of analog dis- continuities in the outputs of cur- rent-switching d/a converters, many users erroneously assume two straight-forward approaches will solve the problem. at the in- put, minimizing time skew among the data bit inputs will be a use- ful technique. at the output. the use of a filter may also appear to be a neat "solution" to the problem. unfortunately. no amount of time alignment on the input bits will overcome the physical laws associated with the propogation delays of saturated logic discussed earlier. in addition, a filter designed for eliminating the "glitch" at the major carry point will not be optimized for transients at other points of the output, nor will it change the relationship of transient amplitudes; this is because the glitch is a function of signal dyna- mics. as a result, a multitude of intermodulation products are form- ed; some of these 1m products ap- pear in the video pass-band as spurious signals, and increased noise level. besides these considerations, no amount of minimizing time skew analog devices ac characteristics dgm-1040 acquisition time sample rate (max) sample delay ttl ecl 15 nsec 30 mhz 10 nsec 6 nsec . i4i 003/0~ dgm-10ao 75 nsec 11 mhz 10 nsec 6 nsec ~ droop rate harmonic distortion feedthru rejection pedestal residual glitch output noise level 8 my/usee >60 db >60 db 10 mv 30 mv 0.2 mv (ams) see fig, 2&3 s~ fig. 2 , my/usee >60 db >70 db 2 mv $"" fig. 1 20 mv s""fiq.1 0.1 mv (rms) dgm-1040 & dgm"1080 dc characteristics gain offset offset drift linearity current source current current sink current .975 adjustable to zero 1 00 ppm/oc :1:0.01% 7.5 ma max 19 ma max analog input characteristics input voltage i:2 v input impedance 1 megohm input bias current 0.05 na analog output characteristics output voltage (no load) :1:2 v output current :!:so ma output impedance 50 ohms deglitch strobe character istics optionally either of the following: ttl single line input "0" = track "1" = hold ecl 2 line complementary "0" = track "1" = hold 0 to +0.4 v 2 standard +2.4 to +4 v ttlload! -1.7 v the.e inpu,," a'e ".ch terminated -0.8 v wit" a 330 ohm pull- down ,a~l~tor to .5.2 v. power requirements +15 v @ 100 ma w/o current source connected -15 v @ 100 ma w/o current source connected +5 v @ 20 ma } ttl input option -5.2 v @ 80 ma -5.2 v @ 24 ma ecl input option. physical characteristics package size 2.3" by 2.3" by 0.43" 58 mm by 58 mm by 11 mm weight pins case 3 oz ~5 grams 0.040 diameter gold plated diallyl phthalate per mll-m-14 type sdg-f obsolete
~oop ~ua" glitch --,---- i fig, i dgm output - dc input 08/25/94 15:01 '5"9106680101 dgm f pedestal. output with dc input? .-. ., oeglitch 1 -1- mold input "0" tract( oil. cata changing data input st~adt glitch period ~ , ~ analog devices degl.iter ~ input:l j -"- 1 anal.ex; outi"ijt of dia final second vdlue initial. val.ue ani.log out of dgm 1 ~ acouistion i tiioie t 1"/. of final. val.ue initial val.ue -- j l sample "i r de:l.oi.y dgm fig,2 output - d/a input 0.' i", ~t "., i',. at 7~ .s o.l~ ~ 0.2 : a ~ dgn-ioeo oco t."e ii' o.i~ is u it 01 '" 0 o' .. o:oe 0.07 o.o~ 0.0' 0.0. 003 0.0l o.oj 0.00 0 00 " 20 73 100 ". .couisit,on tint (n"(,1 fig, 3 acquisition ti~e v$. sli:ttung accuracy .11 .... 0" l. fl , j 1 .11 .. '0 w , 1 ,. ::: oono. "c. :: ~',~a.a. , j ""'" .'. .. ' ::: ~: . ..~,~ i i ~ '000 ---jl",o :~..j j-. l i--- ..,. :..j. , "..'" ,'o.m ." ... , . .,> ..m;, ...c ..,.c" 00 .01 uu "l ,...au". '. t.uc ""', ...0.. '.f ac,,'co, . ".,.,,"". ,. '..cotoc'" uc ,. ."".",.,. loa '" r.."". . , ..au.. . ..0';0" .~ -:-7.:'. . ,"ou.' o.i 0.' ;i 3 g 0.0 ~ ? 0.< 8 .. '" -' ~ ol .. g i'r. 141 004/005 and/or filtering the output will overcome the output voltage limi- tations imposed by internal switch- ing transistor saturation. an optimum solution to the problem of glitches would cause the glitch to remain constant, re- gardless of the transition points on the input data. as an example, it should remain the same for the transition from a 000 000 001 to 1 000 000 000; as it is for the transition trom 1 000 000 000 to 1 000 000 001; or any other two input words. ideally, an optimum solution to the glitch problem would also permit using the full current drive capabilities ot the current-switch- ing d/a converter in both bipolar and unipolar modes ot operation. the purpose of the computer labs dgm modules is to reduce the amplitude of the glitch to an accept- able level, and more importantly, to provide a constant-amplitude glitch. this will hold the area under the curve at a constant value; the modules are not intended to get rid of all glitches per se. when the area under the trans- ient curve is held constant, the fre- quency spectrum of the glitch is a fine line, i.e.. a single-line spectrum at the sample rate frequencies. and harmonics of the sample frequency. the deglitcher circuits effect. ivery eliminate the intermodulation products discussed earlier. when they do. the sin ratio approaches that of an ideally-quantized signal. where the rms noise is q/ v'l2. when frequencies above nyquist are filtered out. the dgm modules also in- corporate an internal adjustable current sink. to adjust the d/a out- put for bipolar operation. in ad- dition, an internal voltage shifter consisting of a current source and a precision resistor allows using the bipolar output drive capabilities of the dfa converter for unipolar positive applications. these fea- tures permit ov to +2v unipolar outputs. an internal buffer amplifier buffers output loading from the d/a module. permitting a constant so.ohm output impedance. non,: ado."onoi ,nfo 08/25/94 ..' strobe ..j c( z .. 0 -0 ... gl:n <;>:: 'c; ~q ... ... 0 strobe 15:02 'a'9106680101 analog devices ~ 005/005 13.i:i,cow"on vi ... :> c1. ~ ..j < r- ia c ~ .... i- ci') c!) i>l a:: 14 output mds - oelis ~ .... (i) ... .... cia converter clock offset adjust 1000 -1 -j l 1:1 1'5 i-- (mini -is v .~ bipolar analog output so okllll 0.1 v no-pi line so a v 0 iop~[tti ' ~i,4 v (p-pi co :501\. sett\,ing tii.'e: . 20 ns "'.!lox, update rate - 30 mhl distortion < 0,1 '/, l.!ioiige signal banowidths up to 15mi1z ultra fast oeglitched cia configuration ref'n +v ,refout 4)0"- t.4dsl-0825 or mdsl- 1035 cia converter iout !iv ana\,og signal 17 , 1600ai . 20 7sji. ogm-1040 deglitch modui..e 11 output: 0 to +i volt into 1s ji. settling time' 20 ns maj(. sample: !la-te' ii whz diff, gain ~4"1, '881t51 ~ 2 ":t. (9 bit51 2 i % 110 bits) dii'i'. phase: 1: 2 eeg. |
